The present invention relates to electron beam lithography for writing a circuit pattern on a semiconductor substrate using electron beam, particularly to a multi-electron beam exposure method and apparatus using multiple electron beams.
Electron beam lithography for writing a circuit pattern directly on a semiconductor substrate using electron beam s is anticipated to make a great contribution as a next-generation writing art for a medium-to-low volume production of a wide variety of products because this art is capable of writing a submicron semiconductor circuit pattern and does not require use of a high-priced pattern projection mask.
However, a substantial improvement in the writing speed is essential for commercial widespread use of the art of writing by electron beam. In recent years, high-speed multi-electron beam exposure methods based on multiple electron beam s have come to be proposed for the improvement in writing speed.
For example, the Japanese Laid-Open Patent Publication No. 2000-243337 discloses a multi-electron beam exposure method wherein multiple electron beams formed by an aperture array are deflected by a common main deflector and sub-deflector, and a desired pattern is exposed on a sample. Other method of forming multiple electron beams includes a great variety of arts such as the method for arranging multiple electron sources and the method for combining multiple electron sources and aperture arrays.
Many of these proposed methods, however, may produce two-dimensionally arranged spot beams because of its simple configuration, and the writing methods are practically the same. Referring to the aforementioned Japanese Application Patent Laid-Open Publication No. 2000-243337, the following describes a specific writing method when multiple electron beams are produced in a 64×64-beam array of a 4-μm pitch.
Multiple electron beams arranged are collectively deflected by a common sub-deflector and are each raster-scanned within the scope of 4 μm square.
This allows a 4 μm square region to be exposed to each electron beam. So the 256 μm square tetragonal regions (sub-field) can be exposed in parallel as a whole. Upon termination of the exposure on 256 μm square region as one of these regions, all the electron beams are moved 256 μm collectively in the X-axis direction (horizontally) by the main deflector in such a way that the 256-μm region can be exposed again by the sub-deflector.
If this operation is continued within the range where deflection can be achieved by the main deflector, exposure is applied to the oblong region (main field) having a width that can be deflected by the main deflector. Thus, if this main field exposure operation is repeated while the sample stage is moved in the Y-axis direction (longitudinal direction), then it is possible to expose the slender stripe region having a main deflection width.
Exposure of all the surfaces of a sample requires all sample surfaces to be partitioned into stripes, then writing of stripes should be performed while the sample stage is moved in the X-axis direction. This method enables parallel writing of 4096 electron beams, and therefore ensures higher writing speed than the prior art method, although each beam is a spot beam.
One of the problems in achieving the aforementioned exposure method is the pattern data generation method for controlling irradiation of each electron beam in conformity to a predetermined writing speed. For example, if a pattern is resolved into 16 nm square pixel and a maximum of 10 ns exposure time is assigned to each pixel, it is necessary to generate data at a speed as high as 409.6 Giga-Bytes per second in order to keep up with the writing speed. This data speed is equivalent to 10,000 times that of the ordinary TV display. This speed can be achieved if the semiconductor circuit pattern is to be expanded in a bit map form in advance and stored in a high speed storage circuit, and is to be read out the time of writing.
However, this requires an extra-high speed storage circuit having a massive capacity of as much as 2400 Giga-Bytes that stores the pattern having a maximum of about 25 mm square. In other words, if the data is to be stored as bit map data in advance, it is necessary to provide a high speed storage circuit having a massive capacity amounting to much as 2400 Giga-Bytes.
When the CAD data of excellent compression rate is to be stored and real-time expansion into the bit map data is to be performed at the time of writing, it is necessary to install a data expansion device having a speed 10,000 times that of the ordinary TV display.
The Japanese Laid-Open Patent Publication No. Hei 07-273006 discloses a configuration wherein bit map data is generated in advance and is stored in multiple large-capacity disks. Further, the Japanese Application Patent Laid-Open Publication No. 2001-76989 discloses a configuration where dot control data is generated at a high speed by multiple expansion sections. However, these proposals fail to prevent the size of the equipment from being increased due to the aforementioned reasons.